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4M x 4-Bit Dynamic RAM 2k & 4k Refresh (Hyper Page Mode - EDO)
Advanced Information * 4 194 304 words by 4-bit organization * 0 to 70 C operating temperature * Hyper Page Mode - EDO - operation * Performance: -50
HYB 5116405BJ-50/-60 HYB 5117405BJ-50/-60 HYB 3116405BJ/BT(L)-50/-60 HYB 3117405BJ/BT-50/-60
-60 60 15 30 25 ns ns ns ns
tRAC RAS access time tCAC CAS access time tAA tRC
Access time from address Read/Write cycle time
50 13 25 84 20
104 ns
tHPC Hyper page mode (EDO) cycle time
* Power dissipation, refresh & addressing:
HYB 5116405 HYB 3116405 HYB 5117405 HYB 3117405 -50 Power supply Addressing Refresh L-version Active TTL Standby CMOS Standby CMOS Standby (L-version) 275 11 5.5 - -60 -50 -60 -50 -60 -50 -60 5 V 10% 12/10 3.3 V 0.3 V 12/10 5 V 10% 11/11 - 440 11 5.5 - 385 288 7.2 3.6 - 252 mW mW mW mW 3.3 V 0.3 V 11/11
4096 cylces / 64 ms 4096 cycles / 128 ms 220 180 7.2 3.6 0.72 144
2048 cycles / 32 ms
* Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh, test mode and Self Refresh (on L-versions only) * All inputs, outputs and clocks fully TTL (5 V versions) and LV-TTL (3.3 V version)-compatible * Plastic Package: P-SOJ-26/24-1 300 mil P-TSOPII-26/24-1 300 mil
Semiconductor Group
1
1998-10-01
HYB 5116(7)405BJ-50/-60 HYB 3116(7)405BJ/BT(L)-50/-60 4M x 4 EDO-DRAM
The HYB 5(3)116(7)405 are 16 MBit dynamic RAMs based on die revisions "G" & "F" and organized as 4 194 304 words by 4-bits. The HYB 5(3)116(7)405BJ/BT(L) utilizes a submicron CMOS silicon gate process technology, as well as advanced circuit techniques to provide wide operating margins, both internally and for the system user. Multiplexed address inputs permit the HYB 5(3)116(7)405 to be packaged in a standard SOJ-26/24 and TSOPII-26/24 plastic package with 300 mil width. These packages provide high system bit densities and are compatible with commonly used automatic testing and insertion equipment. The HYB 3116(7)405BTL have a very low power "sleep mode" supported by Self Refresh. Ordering Information Type 2k-Refresh Versions: HYB 5117405BJ-50 HYB 5117405BJ-60 HYB 3117405BJ-50 HYB 3117405BJ-60 HYB 3117405BT-50 HYB 3117405BT-60 4k-Refresh Versions: HYB 5116405BJ-50 HYB 5116405BJ-60 HYB 3116405BJ-50 HYB 3116405BJ-60 HYB 3116405BT-50 HYB 3116405BT-60 Q67100-Q1098 P-SOJ-26/24-1 300 mil Q67100-Q1099 P-SOJ-26/24-1 300 mil on request on request on request on request P-SOJ-26/24-1 300 mil P-SOJ-26/24-1 300 mil 5 V 50 ns EDO-DRAM 5 V 60 ns EDO-DRAM 3.3 V 50 ns EDO-DRAM 3.3 V 60 ns EDO-DRAM Q67100-Q1101 P-SOJ-26/24-1 300 mil Q67100-Q1102 P-SOJ-26/24-1 300 mil on request on request on request on request P-SOJ-26/24-1 300 mil P-SOJ-26/24-1 300 mil 5 V 50 ns EDO-DRAM 5 V 60 ns EDO-DRAM 3.3 V 50 ns EDO-DRAM 3.3 V 60 ns EDO-DRAM Ordering Code Package Descriptions
P-TSOPII-26/24-1 300 mil 3.3 V 50 ns EDO-DRAM P-TSOPII-26/24-1 300 mil 3.3 V 60 ns EDO-DRAM
P-TSOPII-26/24-1 300 mil 3.3 V 50 ns EDO-DRAM P-TSOPII-26/24-1 300 mil 3.3 V 60 ns EDO-DRAM P-TSOPII-26/24-1 300 mil 3.3 V 50 ns LP-EDO-DRAM P-TSOPII-26/24-1 300 mil 3.3 V 60 ns LP-EDO-DRAM
HYB 3116405BTL-50 on request HYB 3116405BTL-60 on request
Semiconductor Group
2
1998-10-01
HYB 5116(7)405BJ-50/-60 HYB 3116(7)405BJ/BT(L)-50/-60 4M x 4 EDO-DRAM
Pin Names HYB 5(3)16405 4k-Refresh Row Address Inputs Column Address Inputs Row Address Strobe Column Address Strobe Output Enable Data Input/Output Read/Write Input Power Supply Ground (0 V) Not Connected - A0 - A11 A0 - A9 HYB 5(3)17405 2k-Refresh A0 - A10 A0 - A10 RAS CAS OE I/O1 - I/O4 WE
VCC VSS
N.C.
P-SOJ-26/24-1 300 mil P-TSOPII-26/24-1 300 mil
VCC I/O1 I/O2 WE RAS A11 / N.C.
A10 A0 A1 A2 A3 VCC
1 2 3 4 5 6 8 9 10 11 12 13
26 25 24 23 22 21 19 18 17 16 15 14
SPP03454
VSS I/O4 I/O3 CAS OE A9
A8 A7 A6 A5 A4 VSS
Pin Configuration (top view)
Semiconductor Group
3
1998-10-01
HYB 5116(7)405BJ-50/-60 HYB 3116(7)405BJ/BT(L)-50/-60 4M x 4 EDO-DRAM
I/O1 I/O2 I/O3 I/O4
Data IN Buffer WE CAS 4 No.2 Clock Generator
&
Data OUT Buffer
OE
4
10 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11
Column Address Buffers (10)
10 Column Decoder
Refresh Controller
Sense Amplifier I/O Gating
4
Refresh Counter (12) 12 12 Row Address Buffers (12) 12 Row Decoder 4096
1024 x4
Memory Array 4096 x 1024 x 4
RAS
No.1 Clock Generator Voltage Down Generator
SPB03455
VCC VCC (internal)
Block Diagram for HYB 5(3)116405 (4k-refresh)
Semiconductor Group
4
1998-10-01
HYB 5116(7)405BJ-50/-60 HYB 3116(7)405BJ/BT(L)-50/-60 4M x 4 EDO-DRAM
I/O1 I/O2 I/O3 I/O4
Data In Buffer WE CAS & 4
Data Out Buffer 4
OE
No.2 Clock Generator
11 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 11
Column Address Buffers (11)
11
Column Decoder
Refresh Controller
Sense Amplifier I/O Gating 2048 x4
4
Refresh Counter (11) 11 Row Address Buffers (11) 11 Row Decoder . . . 2048 . . .
Memory Array 2048 x 2048 x 4
. . .
. . .
RAS
No.1 Clock Generator Voltage Down Generator
V CC V CC (internal)
SPB02823
Block Diagram for HYB 5(3)117405 (2k-refresh)
Semiconductor Group
5
1998-10-01
HYB 5116(7)405BJ-50/-60 HYB 3116(7)405BJ/BT(L)-50/-60 4M x 4 EDO-DRAM
Absolute Maximum Ratings Operating temperature range ........................................................................................... 0 to 70 C Storage temperature range........................................................................................ - 55 to 150 C Input/output voltage (5 V versions) ................................................... - 0.5 to min (VCC + 0.5, 7.0) V Input/output voltage (3.3 V versions) ................................................ - 0.5 to min (VCC + 0.5, 4.6) V Power supply voltage (5 V versions) ....................................................................... - 1.0 V to 7.0 V Power supply voltage (3.3 V versions) .................................................................... - 1.0 V to 4.6 V Power dissipation (5 V versions) ............................................................................................ 1.0 W Power dissipation (3.3 V versions) ......................................................................................... 0.5 W Data out current (short circuit) ............................................................................................... 50 mA
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC Characteristics TA = 0 to 70 C, VSS = 0 V, tT = 2 ns Parameter 5 V Versions Power supply voltage Input high voltage Input low voltage Output high voltage (IOUT = - 5 mA) Output low voltage (IOUT = 4.2 mA) 3.3 V Versions Power supply voltage Input high voltage Input low voltage TTL Output high voltage (IOUT = - 2 mA) TTL Output low voltage (IOUT = 2 mA) CMOS Output low voltage (IOUT = 100 A) Symbol Limit Values min. max. 5.5 0.8 - 0.4 3.6 0.8 - 0.4 0.2 Unit Test Condition
VCC VIH VIL VOH VOL VCC VIH VIL VOH VOL VOL
4.5 2.4 - 0.5 2.4 - 3.0 2.0 - 0.5 2.4 - -
V
1 1 1 1
VCC + 0.5 V
V V V V
VCC + 0.5 V
V V V V V
1 1 1 1
CMOS Output high voltage (IOUT = - 100 A) VOH
VCC - 0.2 -
Semiconductor Group
6
1998-10-01
HYB 5116(7)405BJ-50/-60 HYB 3116(7)405BJ/BT(L)-50/-60 4M x 4 EDO-DRAM
DC Characteristics (cont'd) TA = 0 to 70 C, VSS = 0 V, tT = 2 ns Parameter Symbol Limit Values min. 2k Common Parameters Input leakage current (0 V VIH VCC + 0.3 V, all other pins = 0 V) Output leakage current (DO is disabled, 0 V VOUT VCC + 0.3 V) Average VCC supply current -50 version -60 version (RAS, CAS, address cycling: tRC = tRC MIN.) Standby VCC supply current (RAS = CAS = VIH) Average VCC supply current, during RAS-only refresh cycles -50 version -60 version (RAS cycling, CAS = VIH, tRC = tRC MIN.) max. 4k 10 10 A A
1
Unit Notes
II(L) IO(L) ICC1
- 10 - 10
1
- -
80 70 2
50 40
mA mA mA
2, 3, 4 2, 3, 4
ICC2 ICC3
-
-
- -
80 70
50 40
mA mA
2, 4 2, 4
Average VCC supply current,during hyper page ICC4 mode (EDO) -50 version -60 version (RAS = VIL, CAS, address cycling: tPC = tPC MIN.) Standby VCC supply current (RAS = CAS = VCC - 0.2 V) Average VCC supply current, during CASbefore-RAS refresh mode -50 version -60 version (RAS, CAS cycling: tRC = tRC MIN.) Average Self Refresh current (CBR cycle with tRAS > tRASS MIN., CAS held low, WE = VCC - 0.2 V, Address and Din = VCC - 0.2 V or 0.2 V)
- -
35 30
mA mA
2, 3, 4 2, 3, 4
ICC5 ICC6
-
1 200 80 70 50 40 250
mA A mA mA A
1
L-version
2, 4 2, 4
- -
ICC7
-
Lversion only
Semiconductor Group
7
1998-10-01
HYB 5116(7)405BJ-50/-60 HYB 3116(7)405BJ/BT(L)-50/-60 4M x 4 EDO-DRAM
Capacitance TA = 0 to 70 C, f = 1 MHz Parameter Input capacitance (A0 to A11) Input capacitance (RAS, CAS, WE, OE) I/O capacitance (I/O1 to I/O4) Symbol Limit Values min. max. 5 7 7 pF pF pF - - - Unit
CI1 CI2 CIO
AC Characteristics 5, 6 TA = 0 to 70 C, VCC = 5 V 10 % / VCC = 3.3 V 0.3 V, tT = 2 ns Parameter Symbol min. Common Parameters Random read or write cycle time RAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay RAS hold time CAS hold time CAS to RAS precharge time Transition time (rise and fall) Refresh period for 2k-refresh version Refresh period for 4k-refresh version Refresh period for Low Power Version Read Cycle Access time from RAS Access time from CAS Limit Values -50 max. min. -60 max. Unit Note
tRC tRP tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tT tREF tREF tREF
84 30 50 8 0 8 0 8 12 10 13 40 5 1 - - -
- - 10k 10k - - - - 37 25 - - - 50 32 64 128
104 40 60 10 0 10 0 10 14 12 15 50 5 1 - - -
- - 10k 10k - - - - 45 30 - - - 50 32 64 128
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ms
7
tRAC tCAC
- -
50 13
- -
60 15
ns ns
8, 9 8, 9
Semiconductor Group
8
1998-10-01
HYB 5116(7)405BJ-50/-60 HYB 3116(7)405BJ/BT(L)-50/-60 4M x 4 EDO-DRAM
AC Characteristics (cont'd) 5, 6 TA = 0 to 70 C, VCC = 5 V 10 % / VCC = 3.3 V 0.3 V, tT = 2 ns Parameter Symbol min. Access time from column address OE access time Column address to RAS lead time Read command setup time Read command hold time CAS to output in low-Z Output buffer turn-off delay Output turn-off delay from OE Data to CAS low delay Data to OE low delay CAS high to data delay OE high to data delay Write Cycle Write command hold time Write command pulse width Write command setup time Write command to RAS lead time Write command to CAS lead time Data setup time Data hold time Read-Modify-Write Cycle Read-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time OE command hold time Limit Values -50 max. min. 25 13 - - - - - 13 13 - - - - - - 30 0 0 0 0 0 0 0 0 13 13 -60 max. 30 15 - - - - - 15 15 - - - - ns ns ns ns ns ns ns ns ns ns ns ns ns
11 11 8 12 12 13 13 14 14 8, 10
Unit Note
tAA tOEA tRAL tRCS tRCH tCLZ tOFF tOEZ tDZC tDZO tCDD tODD
- - 25 0 0 0 0 0 0 0 0 10 10
Read command hold time referenced to RAS tRRH
tWCH tWP tWCS tRWL tCWL tDS tDH
8 8 0 8 8 0 8
- - - - - - -
10 10 0 10 10 0 10
- - - - - - -
ns ns ns ns ns ns ns
16 16 15
tRWC tRWD tCWD tAWD tOEH
113 64 27 39 10
- - - - -
138 77 32 47 13
- - - - -
ns ns ns ns ns
15 15 15
Semiconductor Group
9
1998-10-01
HYB 5116(7)405BJ-50/-60 HYB 3116(7)405BJ/BT(L)-50/-60 4M x 4 EDO-DRAM
AC Characteristics (cont'd) 5, 6 TA = 0 to 70 C, VCC = 5 V 10 % / VCC = 3.3 V 0.3 V, tT = 2 ns Parameter Symbol min. Hyper Page Mode (EDO) Cycle Hyper page mode (EDO) cycle time CAS precharge time Access time from CAS precharge Output data hold time RAS pulse width in EDO mode CAS precharge to RAS delay OE setup time prior to CAS Limit Values -50 max. min. -60 max. Unit Note
tHPC tCP tCPA tCOH tRAS tRHCP tOES
20 8 - 5 50 27 5
- - 27 - 200k - -
25 10 - 5 60 32 5
- - 32 - 200k - -
ns ns ns ns ns ns ns
7
Hyper Page Mode (EDO) Read-Modify-Write Cycle Hyper page mode (EDO) read-write cycle time CAS precharge to WE CAS-before-RAS Refresh Cycle CAS setup time CAS hold time RAS to CAS precharge time Write to RAS precharge time Write hold time referenced to RAS CAS-before-RAS Counter Test Cycle CAS precharge time (CAS-before-RAS counter test cycle) Self Refresh Cycle (L-Version only) RAS pulse width RAS precharge time CAS hold time
tPRWC tCPWD
58 41
- -
68 49
- -
ns ns
tCSR tCHR tRPC tWRP tWRH
10 10 5 10 10
- - - - -
10 10 5 10 10
- - - - -
ns ns ns ns ns
tCPT
35
-
40
-
ns
tRASS tRPS tCHS
100k 95 - 50
- - -
100k 110 - 50
- - -
ns ns ns
17 17 17
Semiconductor Group
10
1998-10-01
HYB 5116(7)405BJ-50/-60 HYB 3116(7)405BJ/BT(L)-50/-60 4M x 4 EDO-DRAM
AC Characteristics (cont'd) 5, 6 TA = 0 to 70 C, VCC = 5 V 10 % / VCC = 3.3 V 0.3 V, tT = 2 ns Parameter Symbol min. Test Mode Write command setup time Write command hold time CAS hold time RAS hold time in test mode Limit Values -50 max. min. -60 max. Unit Note
tWTS tWTH tCHRT tRAHT
10 10 30 30
- - - -
10 10 30 30
- - - -
ns ns ns ns
Semiconductor Group
11
1998-10-01
HYB 5116(7)405BJ-50/-60 HYB 3116(7)405BJ/BT(L)-50/-60 4M x 4 EDO-DRAM
Notes All voltages are referenced to VSS. ICC1, ICC3, ICC4 and ICC6 depend on cycle rate. ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open. Address can be changed once or less while RAS = VIL. In case of ICC4 it can be changed once or less during a hyper page mode (EDO) cycle 5. An initial pause of 200 s is required after power-up followed by 8 RAS cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using the internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 6. AC measurements assume tT = 2 ns. 7. VIH (MIN.) and VIL (MAX.) are reference levels for measuring timing of input signals. Transition times are also measured between VIH and VIL. 8. Measured with the specified current load and 100 pF at VOL = 0.8 V and VOH = 2.0 V. Access time is determined by the latter of tRAC, tCAC, tAA, tCPA, tOEA . tCAC is measured from tristate. 9. Operation within the tRCD (MAX.) limit ensures that tRAC (MAX.) can be met. tRCD (MAX.) is specified as a reference point only. If tRCD is greater than the specified tRCD (MAX.) limit, then access time is controlled by tCAC. 10.Operation within the tRAD (MAX.) limit ensures that tRAC (MAX.) can be met. tRAD (MAX.) is specified as a reference point only. If tRAD is greater than the specified tRAD (MAX.) limit, then access time is controlled by tAA. 11.Either tRCH or tRRH must be satisfied for a read cycle. 12.tOFF (MAX.), tOEZ (MAX.) define the time at which the output achieves the open-circuit conditions and are not referenced to output voltage levels. tOFF is referenced from the rising edge of RAS or CAS, whichever occurs last. 13.Either tDZC or tDZO must be satisfied. 14.Either tCDD or tODD must be satisfied. 15.tWCS, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS > tWCS (MIN.), the cycle is an early write cycle and data out pin will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (MIN.), tCWD > tCWD (MIN.) and tAWD > tAWD (MIN.), the cycle is a read-write cycle and I/O will contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition of I/O (at access time) is indeterminate. 16.These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge in read-write cycles. 17.When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM operation: If row addresses are being refreshed on an evenly distributed manner over the refresh interval using CBR refresh cycles, then only one CBR cycle must be performed immediately after exit from Self Refresh. If row addresses are being refreshed in any other manner (ROR - Distributed/Burst; or CBRBurst) over the refresh interval, then a full set of row refreshes must be performed immediately before entry to and immediately after exit from Self Refresh. 1. 2. 3. 4.
Semiconductor Group
12
1998-10-01
HYB 5116(7)405BJ-50/-60 HYB 3116(7)405BJ/BT(L)-50/-60 4M x 4 EDO-DRAM
t RC t RAS VIH
RAS
t RP
VIL t CSH t RCD VIH
CAS
t RSH t CAS t RAL t CAH
t CRP
VIL t RAD t ASR VIH
Address Row Column Row
t ASC
t ASR
VIL
t RAH t RCS t RRH t AA t OEA
t RCH
VIH
WE
VIL VIH
OE
VIL
t DZC t DZO t ODD
t CDD
I/O (Inputs)
VIH VIL t CAC t CLZ t OEZ
Valid Data OUT Hi Z
t OFF
VOH I/O (Outputs) V OL
Hi Z
t RAC
"H" or "L"
SPT03025
Read Cycle
Semiconductor Group
13
1998-10-01
HYB 5116(7)405BJ-50/-60 HYB 3116(7)405BJ/BT(L)-50/-60 4M x 4 EDO-DRAM
t RC t RAS VIH
RAS
t RP
VIL t CSH t RCD VIH
CAS
t RSH t CAS
t CRP
VIL t RAD t ASR VIH
Address Row Column Row
t RAL t CAH t ASR
t ASC
VIL
t RAH t WCS
t CWL t WP t WCH t RWL
VIH
WE
VIL
VIH
OE
VIL t DS
I/O (Inputs)
t DH
VIH
Valid Data IN
VIL
Hi Z
VOH I/O (Outputs) V OL
"H" or "L"
SPT03026
Write Cycle (Early Write)
Semiconductor Group
14
1998-10-01
HYB 5116(7)405BJ-50/-60 HYB 3116(7)405BJ/BT(L)-50/-60 4M x 4 EDO-DRAM
t RC t RAS VIH
RAS
t RP
VIL t CSH t RCD VIH
CAS
t RSH t CAS
t CRP
VIL t RAD t ASR VIH
Address Row Column Row
t RAL t CAH t ASR
t ASC
VIL
t RAH
t CWL t RWL t WP
VIH
WE
VIL t OEH VIH
OE
VIL t DZO t DZC
I/O (Inputs)
t ODD t DS
t DH
VIH
Valid Data
VIL t CLZ t OEA VOH t OEZ
I/O (Outputs) V OL
Hi Z
Hi Z
"H" or "L"
SPT03027
Write Cycle (OE Controlled Write)
Semiconductor Group
15
1998-10-01
HYB 5116(7)405BJ-50/-60 HYB 3116(7)405BJ/BT(L)-50/-60 4M x 4 EDO-DRAM
t RWC t RAS VIH
RAS
VIL t CSH t RCD VIH
CAS
t RP t RSH t CAS t CRP
VIL t ASR VIH
Address Row
t RAH t ASC
Column
t CAH t ASR
Row
VIL t RAD t AWD t CWD t RWD VIH
WE
t CWL t RWL t WP
VIL t RCS
t AA t OEA t OEH
VIH
OE
VIL
t DZC t DZO
t DS t DH
Valid Data IN
I/O (Inputs)
VIH VIL t CAC t CLZ t ODD t OEZ
Data OUT
VOH I/O (Outputs) V OL t RAC
"H" or "L"
SPT03028
Read-Write (Read-Modify-Write) Cycle
Semiconductor Group
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1998-10-01
HYB 5116(7)405BJ-50/-60 HYB 3116(7)405BJ/BT(L)-50/-60 4M x 4 EDO-DRAM
t RAS t RCD VIH
RAS
t RHCP
VIL t HPC t CRP VIH
CAS
t RP t CP t CAS t RSH t CAS t CRP
t CAS
VIL t CSH t ASR VIH
Address Row Column 1 Column 2 Column N
t RAH
t CAH t ASC
t RAL t CAH t CAH t ASC
t ASC
VIL t RAD t RCS VIH
WE
t RRH
t RCH
VIL t OES t OEA VIH
OE
t CAC t AA t CPA
t CAC t AA t CPA t OFF
VIL t RAC t AA t CAC t CLZ
I/O (Output) V OL
t COH
Data OUT 1
t COH
Data OUT 2
t OEZ
Data OUT N
VOH
"H" or "L"
SPT03038
Hyper Page Mode (EDO) Read Cycle
Semiconductor Group
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HYB 5116(7)405BJ-50/-60 HYB 3116(7)405BJ/BT(L)-50/-60 4M x 4 EDO-DRAM
t RAS t RCD VIH
RAS
t RHCP
VIL t HPC t CRP VIH
CAS
t RP t CP t CAS t RSH t CAS t CRP
t CAS
VIL t CSH t ASR VIH
Address
t RAH
t ASC
t CAH
t ASC
t CAH
t ASC
t RAL t CAH
VIL
Row Address
Column 1
Column 2
Column N
t RAD t WCS t CWL t WCH t WP VIH
WE
t RWL t WCS t CWL t WCH t WP t WCS t CWL t WCH t WP
VIL VIH
OE
VIL t DH t DS
I/O (Input)
t DH t DS
Data IN 2
t DH t DS
Data IN N
VIH
Data IN 1
VIL
"H" or "L"
SPT03039
Hyper Page Mode (EDO) Early Write Cycle
Semiconductor Group
18
1998-10-01
HYB 5116(7)405BJ-50/-60 HYB 3116(7)405BJ/BT(L)-50/-60 4M x 4 EDO-DRAM
t RAS VIH
RAS
VIL t CSH t RP
t CP
t RCD VIH
CAS
t PRWC t CAS t CAS
t RSH t CRP
t CAS
VIL t ASR VIH
Address Row Column Column Column Row
t RAD t RAH t ASC
t CAH
t CAH t ASC t ASC
t RAL t CAH t ASR
VIL t RWD t CWD t RCS VIH
WE
t CWL
t CPWD t CWD
t CWL
t CPWD t CWD
t RWL t CWL
VIL t AA
t AWD t OEA t OEH t WP
t AWD t OEA t OEH t WP
t AWD t OEA t WP t OEH
VIH
OE
VIL t DZC t DZO VIH I/O (Inputs) V IL t CAC t RAC VOH I/O (Outputs) V
OL
t CLZ
t CLZ t ODD t DZC
Data IN
t CLZ t CPA
t CPA
t ODD
Data IN
t DZC
t ODD
Data IN
t DH t DS t OEZ
Data OUT
t DH t AA t DS
t CAC t AA t OEZ
Data OUT
t DH t DS
t OEZ
Data OUT
"H" or "L"
SPT03031
Hyper Page Mode (EDO) Late Write and Read-Modify Write Cycle
Semiconductor Group
19
1998-10-01
HYB 5116(7)405BJ-50/-60 HYB 3116(7)405BJ/BT(L)-50/-60 4M x 4 EDO-DRAM
t RC t RAS VIH
RAS
t RP
VIL t CRP t RPC VIH
CAS
VIL VIH
Address
t ASR
t RAH t ASR
Row Row
VIL VOH I/O (Outputs) V OL
Hi Z
"H" or "L"
SPT03032
RAS-only Refresh Cycle
Semiconductor Group
20
1998-10-01
HYB 5116(7)405BJ-50/-60 HYB 3116(7)405BJ/BT(L)-50/-60 4M x 4 EDO-DRAM
t RC t RP VIH
RAS
t RAS
t RP
VIL t RPC t CP t CSR VIH
CAS
t CHR
t RPC
t CRP
VIL t WRH t WRP VIH
WE
VIL VIH
OE
VIL t ODD
I/O (Inputs)
VIH VIL t CDD t OEZ
VOH I/O (Outputs) V OL t OFF
Hi Z
"H" or "L"
SPT03033
CAS-before-RAS Refresh Cycle
Semiconductor Group
21
1998-10-01
HYB 5116(7)405BJ-50/-60 HYB 3116(7)405BJ/BT(L)-50/-60 4M x 4 EDO-DRAM
t RC t RP t RAS VIH
RAS
t RC t RP t RAS
VIL t RCD VIH
CAS
t RSH
t CHR
t CRP
VIL t RAD t ASC t RAH t ASR VIH
Address Row Column Row
t WRP t CAH t WRH t ASR
VIL VIH
WE
t RCS
t RRH
VIL t AA t OEA VIH
OE
VIL
t DZC t DZO
t CDD t ODD
I/O (Inputs)
VIH VIL t CLZ t RAC t CAC t OEZ
Valid Data OUT Hi Z
t OFF
VOH I/O (Outputs) V OL
"H" or "L"
SPT03034
Hidden Refresh Cycle (Read) Cycle
Semiconductor Group
22
1998-10-01
HYB 5116(7)405BJ-50/-60 HYB 3116(7)405BJ/BT(L)-50/-60 4M x 4 EDO-DRAM
t RC t RAS VIH
RAS
t RC t RP t RAS t RP
VIL t RCD VIH
CAS
t RSH
t CHR
t CRP
VIL t RAD t ASC t RAH t ASR VIH
Address Row Column Row
t CAH
t ASR
VIL
t WCS t WCH t WP t WRP t WRH
VIH
WE
VIL t DS t DH
I/O (Input)
VIN
Valid Data
VIL
Hi Z
VOH I/O (Output) V OL
"H" or "L"
SPT03035
Hidden Refresh Early Write Cycle
Semiconductor Group
23
1998-10-01
HYB 5116(7)405BJ-50/-60 HYB 3116(7)405BJ/BT(L)-50/-60 4M x 4 EDO-DRAM
t RP VIH
RAS
t RASS
~ ~
t RPS
VIL t RPC t CP t CSR VIH
CAS
t CHS
~ ~
t CRP
VIL t WRP VIH
WE
t WRH
~ ~
VIL VIH
OE
~ ~
VIL t ODD
I/O (Inputs)
~ ~
VIH VIL t CDD t OEZ
~ ~ ~ ~
VOH I/O (Outputs) V OL t OFF
Hi Z
~ ~
"H" or "L"
SPT03058
Self Refresh
Semiconductor Group
24
1998-10-01
HYB 5116(7)405BJ-50/-60 HYB 3116(7)405BJ/BT(L)-50/-60 4M x 4 EDO-DRAM
Read Cycle
VIH
RAS
t RAS
t RP
VIL t CHR t CSR VIH
CAS
t RSH t CP t CAS t RAL t CAH t ASC t ASR
Row
VIL
VIH
Address Column
VIL VIH
WE
t WRP
t AA t CAC t OEA
t RRH
VIL VIH
OE
t WRH
t RCS
t RCH
VIL t DZC VIH I/O (Inputs) V IL t DZO t CLZ
I/O (Outputs) V
t CDD t ODD t OFF t OEZ
Data OUT
VOH
OL
t WCS t WRP t RWL t CWL t WCH t WRH t DH
Write Cycle
VIH
WE
VIL VIH
OE
VIL t DS
I/O (Inputs) V IL
VIH
Data IN Hi Z
VOH I/O (Outputs) V
OL
"H" or "L"
SPT03036
CAS-before-RAS Refresh Counter Test Cycle Semiconductor Group 25 1998-10-01
HYB 5116(7)405BJ-50/-60 HYB 3116(7)405BJ/BT(L)-50/-60 4M x 4 EDO-DRAM
t RC t RP VIH
RAS
t RAS
t RP
VIL t RPC t CP t CSR VIH
CAS
t RPC t CHR t CRP
VIL t RAH t ASR VIH
Address Row
VIL t WTH t WTS VIH
WE
VIL VIH
OE
VIL t ODD
I/O (Inputs)
VIH VIL
Hi Z
t CDD t OEZ
I/O (Outputs) V OL
VOH t OFF
Hi Z
"H" or "L"
SPT03042
Test Mode Entry
Semiconductor Group
26
1998-10-01
HYB 5116(7)405BJ-50/-60 HYB 3116(7)405BJ/BT(L)-50/-60 4M x 4 EDO-DRAM
Package Outlines Plastic Package P-SOJ-26/24-1 (SMD) (300mil) (Plastic small outline J-leaded)
B
0.8 min 2.64 0.1 3.75 -0.5
0.5
30
0.85 max
7.75 -0.25
1.27 0.51-0.1
0.18 M 24x 15.24
0.1 0.25 A
6.8 0.2 8.63 -0.25
0.2 +0.1
0.25 B 0.18 M B
1)
26
21 19
14
17.27-0.251) Index Marking
A
1) Does not include plastic or metal protrusions of 0.15 max per side
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Semiconductor Group 27
Dimensions in mm 1998-10-01
GPJ05628
1
68
13
HYB 5116(7)405BJ-50/-60 HYB 3116(7)405BJ/BT(L)-50/-60 4M x 4 EDO-DRAM
Plastic Package P-TSOPII-26/24-1 (400 mil) (SMD) (Plastic Thin Small Outline Package (Type II))
0.1 0.05 1.2 max 5 max
GPX05857
7.62 0.13
1.27 0.4 +0.12 -0.1 0.2 M 24x 0.1
0.6 -0.2 9.22 0.2
26
2119
14
1
68 13 1) 17.14 0.13
Index Marking
1)
Does not include plastic or metal protrusion of 0.15 max per side
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Semiconductor Group 28
0.15 +0.06 -0.0
10.05
3
Dimensions in mm 1998-10-01

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